2D and 3D non-volatile memory devices is an area with much ongoing development in methods to improve performance, increase density and reduce die size (cost). As memory layers increase in 3D memory devices, there is an increasing need for die space to occupy the peripheral circuitry for control logic, decoder logic, drivers, sense circuitry, I/O circuits and other memory controller related logic. Hence, there is a need to reduce the die area required for such periphery circuitry in order to reduce the cost of memory devices. With regard to flash non-volatile memory devices (NAND and NOR), the required periphery circuity exceeds upwards of 30%. A significant amount of circuitry is devoted to counting the read and write cycles on a per bit or word basis for the purpose of improving reliability. Additional circuitry is required to provide all the required voltages to various word, bit and gate lines to correctly read and write the memory bits.
Flash memory is a type of non-volatile memory technology that can be electrically erased and reprogrammed. The original principal was based on modifying the stored charge in a floating gate of a transistor (invented by D. Kahng & S. M. Sze, of Bell Labs in 1967). There are two basic types of Flash Memory—NOR Flash Memory and NAND Flash Memory. NOR Flash was invented by Dr. Fujio Masuoka, Toshiba, in the early 1980's—commercialized by 1988—and NAND Flash was also invented by Dr. Fujio Masuoka, in the late 1980's—commercialized by 1995.
NAND flash uses floating-gate transistors for charge storage and is connected in a way that resembles a NAND gate; i.e., several transistors are connected in series, and only if all word lines are pulled high (above the transistors' threshold voltage, Vt) is the bit line pulled low. When the floating gate (charge storage layer) charge is modified, the threshold voltage of the cell (Vt-cell) is changed due to a resistance change; hence, information can be memorized in such fashion. To read, most of the word lines are pulled up above Vt of a programmed bit, while one of them is pulled up to just over the Vt of an erased bit. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed. NAND flash uses tunnel injection for writing and tunnel release for erasing. Flash memory is limited in that although it can be read or programmed a byte or word at a time in a random access fashion, it must be erased a “block” at a time, thereby adding to overhead circuitry and latency. Flash memory is also limited in endurance, with a finite number of erase-write cycles, normally less than 100,000 erase-write cycles. This also adds to overhead in terms of error correction circuitry and redundancy.
FIG. 1 shows an equivalent circuit of a NAND type flash memory device according to the prior art [FIG. 1 of U.S. Pat. No. 7,863,671, assignee: Hynix Semiconductor]. A memory cell array includes a plurality of cell strings connected to associated bit lines, BL1, BL2, . . . Each unit cell string includes a source select transistor (SST), memory cells M1-M32, and a drain select transistor (DST). Each drain select transistor (DST) is connected to the one of bit lines, BLe and BLo. Each source select transistor (SST) is connected to a common source line (CSL). The memory cells M1-M32 are serially coupled between the source select transistor (SST) and the drain select transistor (DST). The number of memory cells included in one cell string is varied depending on the storage capacity of memory device used. The gate of the source select transistor (SST) at each cell string is commonly connected to a source select line (SSL). The source select line (SSL) transmits a string select signal supplied from a row decoder. A drain select line (DSL) transmits a drain select signal supplied from the row decoder. The drain select line (DSL) is connected to the gate of the drain select transistor (DST). The control gates of the memory cells M1-M32 are coupled to word lines WL1-WL32, respectively.
A memory cell includes a tunnel insulating layer, a floating gate, a dielectric layer, and a control gate. In the source select transistor (SST) and the drain select transistor (DST), a first polysilicon layer for the floating gate is in contact with a second polysilicon layer for the control gate via a contact hole passing through the integrate dielectric layer. When the contact resistance between the first polysilicon layer for floating gate and the second polysilicon layer for the control gate abnormally increases, signal transmission is delayed and chip failure occurs, thus causing a significant deterioration in fabrication efficiency.
The increased contact resistance is due to a polymer or a parasitic oxide layer formed while etching of the dielectric layer and remaining due to incomplete removal by an etchant, prior to deposition of the second polysilicon layer. In addition, because the contact between the first polysilicon layer and the second polysilicon layer inherently has a high resistance, a delay in signal transmission of the SSL and DSL and an occurrence of chip failure result.
FIG. 2 and FIG. 3 are prior art comparisons of a NAND type flash memory and NOR type flash memory. The cells in a NOR type memory are connected in parallel as opposed to in series (NAND), and hence occupy more die area (10F2) compared to NAND memory cells (5F2). NOR flash requires higher current than NAND, is faster than NAND and exhibits much better endurance compared to NAND. NAND flash on the other hand provides higher density due to the smaller cell, lower power consumption, and low cost compared to NOR.
The charge storage layer in flash memory may be either a floating gate made of a conductive material or a charge trap made of a non-conductive material that still may hold an embedded charge. FIG. 4 is a prior art drawing comparing a charge trap type flash memory (SONOS) to the originally developed floating gate type of flash memory.
The fundamental circuit in FIG. 1 is representative of either 2D or 3D constructions. A memory device is considered 2D when only one layer of memory cells are present; if more than one layer of memory cells are present in the vertical (z-axis) direction (perpendicular to the normal plane of the substrate), then the device is considered 3D. FIG. 5 [FIG. 2B of U.S. Pat. No. 8,932,955, Assignee: SanDisk Technologies Inc.] is one representation of a 2D NAND construction; FIG. 6-FIG. 8 are prior art representations of 3D NAND constructions. FIG. 6 is a summary chart shown by Sung Wook Park of SK Hynix comparing the four 3D NAND structures from the major memory manufacturers: Toshiba (Japan), Samsung (Korea), SK Hynix (Korea), and Micron (USA). FIG. 7 is an equivalent circuit of Bit-Cost Scalable (BiCS) Technology for 3D NAND Flash Memory promoted by Toshiba. FIG. 8 shows a construction of the Terabit Cell Array Transistor (TCAT) Technology for 3D NAND Flash Memory promoted by Samsung. There are a host of many different constructions for 3D NAND (and NOR) flash memory described in detail in the many prior art patent references.
3D flash memory constructions are such that control logic, decoder logic, sense circuits, I/O circuits and driver circuits necessarily are located as peripheral circuits, thereby increasing the required die area for a given memory design. This necessity for locating the circuits on the periphery of the memory array are illustrated in the prior art, FIG. 9-12. FIG. 9 [FIG. 1 of U.S. Pat. No. 6,906,940, Assignee: Macronix International] illustrates the large area for contact holes required for the independent word lines and bit lines for a prior art 3D memory structure. Peripheral circuits 104 are connected to the word lines and bit lines from layers 100a-100n through corresponding contact holes 102a-102n. For example, lines 100a-100n may represent bit lines from the first, second, third and nth layer of the memory structure, respectively. Since lines 100a-100n of the different layers are independent, then respective contact holes 102a-102n cannot be common. It should be appreciated that the same would be applicable if lines 100a-100n were word lines. Thus, the multitude of contact holes requires a large area and leads to reduced array efficiency. As the number of memory layers increase, the contact area must expand outwards, thereby offsetting density gains achieved through the three dimensional structure. FIG. 10 [FIG. 5 of U.S. Pat. No. 6,906,940, Assignee: Macronix International] is a prior art method to improve the memory capacity by enabling a decoding scheme in which word line and bit line concepts are extended to orthogonal planes associated with common word and bit lines resulting in a dramatic reduction in the number of contact holes. There's no teaching however related to the peripheral circuitry which remains outside the area of the matrix of memory cells and still occupies increasing space as the number of memory layers increases. FIG. 11 [FIG. 5 of U.S. Pat. No. 8,154,128, Assignee: Macronix International] illustrates yet another example of a prior art design showing a periphery region outside the area of the memory array region required for interconnect structures and—although not shown—decoder logic, drivers and other controller related circuitry. FIG. 12 [FIG. 19 of U.S. Pat. No. 8,437,192, Assignee: Macronix International] further indicates the routing of decoder logic to the area outside of the memory array region.
The area for such periphery circuitry can occupy a significant area of the die. For example, Samsung's 128Gb 3b/cell V-NAND Flash was reported in March 2015 to have a die area of 69.9 square millimeters (6.32 mm×10.9 mm) for a 32-layer design. The periphery circuitry area was estimated at 19 square millimeters which is about 30% of the total die area. Source: Andrew J. Walker http://www.3dincites.com/2015/03/samsungs-v-nand-flash-2015-isscc-way-left/
FIG. 14a and FIG. 14b are electrical schematic diagrams (FIG. 1B and FIG. 25, U.S. Pat. No. 8,824,209, assignee: Samsung) of a vertical NAND device according to a prior art. FIG. 15 [FIG. 4 of U.S. Pat. No. 8,437,192, Assignee: Macronix International] is an illustration of the construction of x-axis, y-axis and z-axis conductive lines in a 3D memory device according to a prior art and represents one of many constructions of 3D NAND flash memory devices.